Tag Archives: Transputer

Paradico – “The cube”

September 22, 2009 Axel Leave a comment

This is yet another pretty unknown Transputer module. The silkscreen print says “PARADICO – beheer submodule – BOP 1990”. Well, beheer is Dutch for management, so it was the management submodule for… something.

I got myself 4 of those from my Transputer-Bro’ Mike and after a good year of lying in my cupboard it was overdue to do something with them.
Mike was kind enough to do the basic deciphering of all the traces, links and stuff, so it was basically just building & wireing a front- and back-plane to get them working.

This is how one PARADICO looks like:

Not everthing is readable here but it does the job because the PARADICO is a pretty standard Transputer design. More or less a huge TRAM. So nothing fancy about it:

One T800-25 Transputer
4MB DRAM (4×256)
Some PALs for the memory decoding
Buffers for the links
A 5MHz oscillator
A fuse… just to be safe 😉
Handy jumpers for LinkSpeed and CPUSpeed

IMHO this is actually quite a waste of space but in these days you have to take what you get, right? 😉

Ok, so I ordered 8 DIN41612 sockets and after a day worth of soldering “The Cube” was finished:

“The Cube? It’s not square at all!” you might say. Yes, true, but the specs are all nicely squared so here’s the proof. The Cube has: 2² Transputers running at 5² Mhz, each has its own 2²MB RAM. Voilà, a cube 😉
For the convenience of connecting the cube to more or less any other system, I’ve added a hex-inverter so notAnalyse, notReset & notError can be converted into their “positive” counterparts (in the upper left corner of the picture, next to 3 red jumpers).

This is the ispy output connected to the “Gerlach Card“:

Using 150 ispy 3.23 | mtest 3.22
# Part rate Link# [ Link0 Link1 Link2 Link3 ] RAM,cycle
0 T800d-24 240k 0 [   HOST    1:0    …    … ] 4K,1 1024K,3;
1 T800d-25 1.8M 0 [    0:1    2:0    3:0    4:0 ] 4K,1 4096K,4;
2 T800d-25 1.8M 0 [    1:1    …    …    … ] 4K,1 4096K,4;
3 T800d-24 1.8M 0 [    1:2    …    …    … ] 4K,1 4096K,4;
4 T800d-24 1.8M 0 [    1:3    …    …    … ] 4K,1 4096K,4;

And if you happen to stumble over a Pradico yourself, here’s the pinout of the front DIN41612 connectors:

          X  A32 C32   X
        GND  A31 C31  GND
 UpNotError  A30 C30  DownNotError
 UpNotAnaly  A29 C29  DownNotAnaly
 UpNotReset  A28 C28  DownNotError
        GND  A27 C27  GND
         X   A26 C26   X
   LinkOut0  A25 C25  LinkOut1
    LinkIn0  A24 C24  LinkIn1
        GND  A23 C23  GND
        GND  A22 C22  GND
         X   A21 C21   X
   LinkOut2  A20 C20  LinkOut3
    LinkIn2  A19 C19  LinkIn3
        GND  A18 C18  GND
         X   A17 C17   X
        GND  A16 C16  VCC
        GND  A15 C15  VCC
         X   A14 C14   X
         X   A13 C13   X
         X   A12 C12   X

JP1:
1 LinkSpecial
2 Link0Special
3 Link123Special

JP2:
1 ProcSpeedSel0
2 ProcSpeedSel1
3 ProcSpeedSel2

Next up: The Cube moves into the Tower of Power… when other more important things are done.

Caplin Cybernetics

Caplin Cybernetics i860/Transputer cards

August 26, 2009 Axel Leave a comment

Caplin Cybernetics (just Caplin for short) was one of those many UK based (London to be exact) companies building Transputer based high-performance systems. Caplin seemed to be specifically concentrating on providing Transputer technology for DEC systems, namely VAXen.

As of now, I do not know much more about Caplin, but I know there are still some former employees around and I’d be happy to learn more about the company as well as the systems I’m going to describe further down.

By a lucky indecent I got my little greedy hands onto 2 different Caplin systems. Both connecting Transputer (networks) to a mighty Intel 80860XP.
While these boards have i860’s on them I’ve put them into this Transputer category, as they were meant as math accelerator for Transputer networks, not the other way round like the DSM860 boards, which used Transputers mainly for networking.

I don’t have any documentation for those boards but I hope to get them working as soon I figured out how to connect to the Transputers, find out more about the memory-mapping and found a way how to read those damn Bipolar-PROMs.

That said, from here everything is just wild speculation, assumption and finger-in-the-air-guessing – If you know more/better: Let me know please!

I’m specifically looking for the document called “Caplin XPR Series Technical Overview”. If you still have a copy or you do know somebody who might: I’d be very happy to hear from you!

HXI860

The HXI860 seems to be the earlier implementation of a Transputer-to-i860 board. It is a quite late i860 implementation though, featuring the first incarnation of the i860, the 860XR, predecessor of the 860XP.

A picture says more than a 1000 words: The HXI860 in full view

Let’s start with the left side of the board. The picture is a bit blurry (sorry) but it’s enough to identify what I’m going to talk about:

Starting on the left there are many blue 2-row pin connectors. This seems like a job for long winter evenings to find out which pin is connecting to what.
Then there are the 3 “golden boys” next to the connectors: From top down those are 1 T800-25 and two C004 linkswitches. Above the T800 there’s 4MB for his own use.
Then there are two FPGAs, one with the AT&T logo (ATT3020) and one more familiar XILINX XC2064, both getting their programming from an Xilinx 1736A PROM.
In the top-right corner the heavy-wight-champion i860XR (40MHz) surrounded by lots of buffers and GALs. The long DIP ICs on the right edge are IDT73210 octal transceivers with parity checking.
Rightmost are the connectors to the DEC Q-Bus… luckily only power & GND are taken from there, so you don’t necessarily need a VAX to use the board.

The right side of the board looks like this:

Ignoring the lurking C004 and Xilinx CPLD the leftmost black square IC is an T222C-17 which most likely controls the initial C004 configuration. He gets his code from two ICT 27CX642 which are quite strange devices: Made like CMOS EPROMS they use differential memory cell techniques to provide bipolar-prom speed. No idea how I will be able to read them out with my standard EPROM programmer.
Also, there’s a “6bit” dip-switch next to the T222 which I was told will be used to configure the link routing… let’s see what I will figure out by try’n’error.
The other four square ICs are 2Kx16 dual-ported RAMs (IDT7133). Four of them makes 64bit… well, that the i860 memory bus interface.
Last but not least there’s a long DIP IC above the DP-RAM… it’s an C012 Transputer link-adapter. So one Transputer link must be connected here, converted into 8-bit parallel. Could it be that they connected the 64-Bit RAM of the i860 via a transputer-link? (shudder)
Ok, and obviously there are 8 SIMM slots for i860 RAM… parity RAM required.

XPR201

This much bigger board seems to be the successor to the HXI860 and I was told it was the fastest i860 board Intel ever tested. Also this seems to be a prototype and was never officially sold.
It now features a 50MHz i860XP (fastest i860 available), two instead of one T800 but no C004 at all. Also the communication between the Transputer(s) and the i860 seems to be fully memory-mapped and no C012 is involved.

Here’s the full-view:

Let’s go into detail… the “Transputer side” for a start:

The connector at the top-right edge is yet of unknown type.
Below this, there are 2 T805-25, each having 4MB of RAM. Two AM27S33 4Kx4 bipolar PROMs (flanking the RAM to each side) seem to offer the 4K boot-code.
This board, too, has a 6bit dip-switch. Again, no idea yet what it does.

The most space in this picture is used by the much more sophisticated i860-to-Transputer interface, which is so complicated that it needs a diagram for itself (Thanks to Mike B. for beautifying this!):

Eight(!) 4Kx16 IDT7024 dual-ported SRAMs are used to convert the i860’s 64bit bus to the Transputer 32bit bus – most likely they’re part of the “DMA engine”, too.

For doing this you normally only need 4 of them, but as you can see on the above diagram, Caplin chose to use the two T800 independently, so each Transputer has his own 16k SRAM directly connected to the i860.
Then, each Transputer is also connected to a 1MB VRAM bank (consisting of eight HM538123 having 128K word x8 DRAM and 256-word x8 Serial RAM). I was told the serial-side is connected to the Transputer, the parallel-side to the i860. Behind the VRAM is the “DMA engine” most likely the array of XILINX FPGAs you can see on the upper edge of the picture below.

The reason for this “over engineered” design most likely was, that you could use the SRAM for small but very fast read/write operations, while you would use the VRAM for bigger chunks of data.

The lower-edge (“i860 side”) overlaps a bit with the above picture of the “Transputer side”:

Again, like on the HXI860, lots of IDT73210 octal transceivers, the 4 XILINX FPGAs (the “DMA-engine”, also fed by 1736As) and a huge array of GAL/PALs doing the bus-handling.
Then there’s the i860XP (50MHz) hidden under a heatsink.
A bit below is a 16-positions dial – no idea what it does. First thing coming to my mind: RAM timing.
Finally even more buffers connected to 8 SIMM slots (the i860 private RAM, Parity-only again).
The blue connector on the bottom edge is meant to connect to a 2 digit, 7 segment display which I have on a second board I own.

AVM T1

Hacking the AVM T1

June 21, 2009 Axel Leave a comment

It was inevitable… the biggest system AVM built was the “T1”, a 30 channel ISDN controller in a sleek 1U 19 inch case of which nothing more than the above marketing picture seems to exist.
One fine day I had to had one – and today is the day!

I was able to find a AVM T1 on ePay which was not very well advertised so I had no “professional competition”. Even I didn’t spent a fortune it was a bit of gambling because I didn’t knew what to expect.
Besides AVMs own T1 PDF manual there’s next to nothing available in the Web – So this section is yet another WWW-exclusive brought to you by geekdot.com 😉 (Ok since 2009 others discovered this page and also this cheap entry into the wonderful world of multi Transputing)
Still, the docs said “a Transputer network with 9MB RAM” so I couldn’t go completely wrong. That said, I was expecting SMD T400s at AVMs usual sluggish speed…

First look

When the box arrived first thing was getting out good ol’ screwdriver and open the case…

…and I was very surprised:

A socketed T425 – so that’s another easy upgrade then.
An external power supply (48V)! That’s strange but also neat – no noise and next to no heat in the case itself
Also, the board is very small… lot’s of room left in the case.

That’s done by intention as you could buy the T1-B, where “B” stands for the “Booster Board”, yet another board with 4 more Transputers and another 8MB of RAM giving a total of 7 Transputers and 17 Megs of memory. Quite a setup for just an ISDN controller.

Sniffing around

Ok, this beast has to do something better than handling 30 boring B-Channels… Mandelbrot for example 😉 So let’s see how this thing is/was supposed to speak to the outside world.

The manual is talking about an ISA or PCI controller-card which will be connected to a 9-pin Sub-D connector. Having a closer look to the mainboard where that connector is seated I discovered some other old friends: AM26C31 and AM26C32.
Aaaaalrighty, RS422 time… that’s the same way my Tower of Power is transmitting its data. So I can use my TTL-to-RS422-converter I’ve built for the Gerlach card.

Out goes the multimeter and after a while I figured out the the traces on the board. For a better understanding, here’s the “map”:

Marked by the red arrows are the three Transputers: T1, a T425-25, is the “application processor” while T2 and T3 are more simple T400-20 handling the ISDN subsystem.

The yellow arrows mark the four links of the T425 – which is probably the reason why AVM used a 425 vs. their usual T400: this time they really needed 4 links.
Link0 is connected to the 9-pin sub-D connector (via the RS-422 transmitters/receiver) for interfacing to the PC.
Link1 and Link2 are directly connected to the T400s.
Link3 goes to the connector on the lower edge of the board. I bet this is where the “booster board” would be connected… not a hard bet, I admit.

The pinout for the 9-pin sub-D connector (female) is:

 1 Link0-IN -
 2 N/C
 3 Reset-IN +
 4 N/C
 5 Link0-OUT +
 6 Link0-IN +
 7 Reset-IN -
 8 GND
 9 Link0-OUT -

As Link0-IN and Reset-IN are routed through two separate 26c32 I assume there might be more differential signals available. If time allows I’ll dig deeper on this matter.

Do something Gromit!

Well then… a cable was built in a couple of minutes – some cursing and swearing about the differential polarity and then the exciting moment came: Let’s see if it’s really so easy again!

It is! And here’s the ispy output for the T1 (connected to the “Gerlach card”):

Using 150 ispy 3.23 | mtest 3.22
# Part rate Link# [ Link0 Link1 Link2 Link3 ] RAM,cycle
0 T800d-25 288k 0 [   HOST    …    …    1:0 ] 4K,1 1024K,3;
1 T425c-20 1.6M 0 [    0:3    2:0    3:0    … ] 4K,1 4092K,3.
2 T400c-20 1.7M 0 [    1:1    …    …    … ] 2K,1 1022K,3.
3 T400c-20 1.8M 0 [    1:2    …    …    … ] 2K,1 4094K,3.

Some remarks about this:

9 MB is true. The “application processor” (T1) got 4MB while the two T400s got 1 (T2) and 4 MB (T3, obviously connected to the SIEMENS Munich32 Über-ISDN controller).
While the built-in T425 is spec’ed for 25Mhz it’s just running at 20MHz… what a waste of bang… and what an opportunity for improvement :->
The linkspeed is at maximum… which one would expect with directly connected links. But with AVM you’ll never know 😉
The RAM-speed is pretty good (compared to what they did to the B1) – even they just used 70ns RAM.

Next up: Having fun with Mandelbrot! Having just T4xx Transputers it can only use the integer algorithms (i.e. no floating point) but who cares for a quick start?!

It’s working and showed another nice gadget: LEDs! Each Transputer has a tiny SMD-LED connected to it’s Link-Out.
So having the T1 underneath the table I have quite a nice light-show while the three are working their a** off 😉

If you happen to have no access to a RS422 converter: Never say die!
Like said above, there’s still Link3 available – normally meant for the booster-board – and it’s pure TTL. All you need is a somewhat non-standard plug to this connector. Be creative but don’t forget that unbuffered link connections only allow a distance of a couple of inches/centimeters!

The pin-out (so far) is, counting from left to right:

 1 - 5V VCC
 2 - T1 Link3 OUT
 3 - T1 Link3 IN
 4 - RESET
 5 - T3 Link1 OUT
 6 - T3 Link1 IN
 7 - GND

[UPDATE 11/14/10] Again, with some ePay-Luck I got another T1… and it again was some kind of lottery… and I had luck! This time it’s a T1-B!! This means, the “booster board” is installed. So opening the case, it looks like this. On the right the normal T1-board, to the left, “da mighty booster board” 😉 I’ll call it “BB” from here…

As expected, it’s connected via Link-3 of the T1 Board. On the lower edge of the picture you can spot the power-supply “module”. It’s longer than in the T1 configuration and provides 3.3V/GND to the BB, i.e. the BB is 3.3v only!!

Here’s the BB alone:

All in all the BB is more modern than the T1-board. Very suspicious are the JTAG connector on the lower left having its lines connected to a EEPROM (AT28V256, right edge of the BB board, above the row of RAMs). Further up, left to the CPU nearby is a pad with the lable “Boot from ROM/Link”. I wonder what the default is and what’s inside that EEPROM – will investigate later.

Most importantly the BB board features 4 ST20450 processors, which aren’t INMOS products anymore. They were designed by ST after they bought INMOS. For short, the ST20450 is a T425 on steroids. More on-chip RAM (16K), higher clocking (40MHz) and some more instructions.
Each ST20450 has its own 2MB of RAM and a GAL handling the memory etc.. Here’s a close-up of a single ST20450 “module”:

Mind the careful markings/labels on the board. The CPUs are numbered (“Processor 3”) and there are pads for Links etc.

Finally, I currently have no tools to check/use ST20450 processors. ispy finds the Transputers on the T1 board but freaks-out when it pings the ST20s.

Here’s another new addition: A picture of the official T1-PCI interface. It contains a PCI-controller (the big IC) and a XILINX FPGA… probably containing a synthesized C011.

UPDATE:

Jonathan Schilling also ~~plays~~ played around with an AVM T1 on his page including the original ISA controller card… and he~~‘s making~~ made very good progress!
[2015, Jonathan quit ‘the scene’ and handed over all his equipment… further on, it seems in 2020 he closed his pages]

Another UPDATE [2017]:

Just got another T1 off ePay… surprisingly it contained yet another board-design. I’ll call it the “non-booster layout“. This board has no connectors for the booster-board and missing the regulator below the DC/DC converter – no need for 3.3V.

TODO:

Change the T425
~~Make the 30 front-panel LEDs blink~~
Figure out for what the female 15pin sub-d connector is good for (not mentioned in the manual)

Here’s how to access the LEDs at the front – thanks to Michael Brüstles research:

typedef unsigned long int u32;

/*
 *  addr XXXX-XXXX-X111-XXXX-XXXX-XXXX-XXXA-AA00
 *    
 *  wr                               0-01    __ EN __ __-__ __ __ SY
 *  wr                               0-10    08 07 06 05-04 03 02 01
 *  wr                               0-11    16 15 14 13-12 11 10 09
 *  wr                               1-00    24 23 22 21-20 19 18 17
 *  wr                               1-01    SC ST 30 29-28 27 26 25
 *
 *  rd                               0-01    readable ... content unknown
 */

int main( void ) {

    u32 *p = (u32*)0x80700000UL;

    p[ 1 ] = 0x40;  /* enable all leds 0x40 & Sync 0x01 */
    p[ 2 ] = 0x05;  /* Led01-Led08 */
    p[ 3 ] = 0x00;  /* Led09-Led16 */
    p[ 4 ] = 0x3F;  /* Led17-Led24 */
    p[ 5 ] = 0x92;  /* Led25-Led30, System, S-channel */

    return 0;
}

Tower of Power

February 28, 2008 Axel Leave a comment

Having the “Gerlach card” running, I was looking for ways to create something Transputers were made for: A farm, grid, network, cluster – call it what you like.

By a lucky incedent I was able to make contact to some people at DESY, which is one of the world’s leading accelerator centres. DESY develops, builds and operates large accelerator facilities, which are used to investigate the structure of matter. It’s comparable to the CERN accelerator in Switzerland.
I’ve learned that they were on schedule to switch-off a part of their accelerator, namely ZEUS (German), as all the planned research-protocols were finished… and I’ve learned that they use(d) several transputers for data aquisition and real-time analytics!
So after 2 years of shmoozing and sending ASCII-art flowers in mails, I was allowed to give their transputers a new home (else they would have been destroyed – oh my!).

I was surprised to see, that there was not the amount of transputers used as I would have expected (hundreds?). So no wonder they were able to replace the transputers by one single Linux box for the last year of the project, running the transputers as hot-standby backup.
But I also got all their spare-parts and everything else… a good start.

The original system consisted of 12 transputers, each on a TRAM, 4 of those sitting on a custom made TRAM-board called “TRAMWAY” which looks like this:

It’s not really worth calling it a board – It’s mainly a TRAM carrier with RS422 drivers for each link. The links for the TRAMs are hardwired, so TRAM1 has one “down link” (i.e. from the host or another card) connected to link0. Link1, 2 & 3 are connected to TRAM1, 2 & 3 respectively.

6 of those TRAMWAYs are currently sharing a case making it The Tower Of Power:

As you can see I stacked some TRAMs (Size-1 TRAM on a size-2 TRAM) to squeeze in the maximum number of TRAM… power to the tower, man!
Here’s another one showing the ToP with its host, an Intel LP486:

This is how the full power looks like in ‘ispy’:

Using 150 ispy 3.23 | mtest 3.22
# Part rate Link# [ Link0 Link1 Link2 Link3 ] RAM
0 T425b-20 239k 0 [   HOST    …    …    1:0 ] 136K.
1 T805b-25 1.5M 0 [    0:3    2:0    3:0    4:0 ] 4100K;
2 T800d-20 1.8M 0 [    1:1    5:0    6:0    … ] 1028K;
3 T800d-20 1.8M 0 [    1:2    7:0    8:0    … ] 1028K;
4 T800d-20 1.8M 0 [    1:3    9:0    …    … ] 1028K;
5 T800d-20 1.6M 0 [    2:1   10:0   11:0   12:0 ] 1028K;
6 T800d-20 1.6M 0 [    2:2   13:0   14:0   15:0 ] 1028K;
7 T800d-20 1.6M 0 [    3:1   16:0   17:0   18:0 ] 1028K;
8 T425b-20 1.8M 0 [    3:2   19:0   20:0   21:0 ] 132K;
9 T800d-20 1.6M 0 [    4:1   22:0   23:0   24:0 ] 1028K;
10 T805d-20 1.8M 0 [    5:1    …    …    … ] 1028K;
11 T800c-17 1.8M 0 [    5:2    …    …    … ] 2052K;
12 T800c-20 1.8M 0 [    5:3    …    …    … ] 1028K;
13 T800d-20 1.8M 0 [    6:1    …    …    … ] 1028K;
14 T800d-20 1.8M 0 [    6:2    …    …    … ] 132K;
15 T800d-20 1.6M 0 [    6:3    …    …    … ] 132K;
16 T800d-20 1.8M 0 [    7:1    …    …    … ] 1028K;
17 T800c-17 1.7M 0 [    7:2    …    …    … ] 2052K;
18 T800c-20 1.7M 0 [    7:3    …    …    … ] 1028K;
19 T425b-20 1.8M 0 [    8:1    …    …    … ] 132K;
20 T425a-20 1.8M 0 [    8:2    …    …    … ] 132K;
21 T425b-20 1.8M 0 [    8:3    …    …    … ] 132K;
22 T805d-20 1.8M 0 [    9:1    …    …    … ] 1028K;
23 T800d-25 1.8M 0 [    9:2    …    …    … ] 2052K;
24 T800d-20 1.8M 0 [    9:3    …    …    … ] 1028K;

Das Transputerbuch

February 28, 2008 Axel Leave a comment

There was one major german book about transputers called “Das Transputerbuch”, written by Uwe Gerlach (ISBN 3-87791-019-X).
What made this book special was that it included an unpopulated 8-bit ISA card for a transputer and 1MB RAM, fully B004 compatible.
Additionally, there were schematics provided to build a host-adapter for several homecomputers of that time (C64, Apple II, ATARI ST and Commodore Amiga).

I was able to get one book off ePay which was still includung the printed circut board and a 360k floppy containing some sample sources and a rudimentary assembler.
So I’ve polpulated it, found some mistakes Gerlach made and made it somehow run.

This is how the card looks

It’s design is pretty simple – at least compared to the efforts been taken with the i860 cards on this page. The simple design is also because the Transputer has nearly everything included… so what you see is:

The right half is the ISA-bus and link interface. The rightmost and longest IC is a C012 connecting the 8-Bit ISA bus to link0 of the Transputer. Everything else are buffers & drivers.
The left half is -besides the Transputer itself- just 1MB RAM and some address-logic. The card would also work without having this side populated using the internal 2 or 4k of the Transputer.

C’est ca. As said, prety simple.

The mentioned bugs of the card are:

The orientation of U11 and U12 are wrong on the print on the PCB and in the book, check the photo for them.
There are no holes for the capacitor near to U28, you will have to solder it to the corresponding pins on the back of the PCB.
The crystal oscillator U12 has its pin-1 not-connected, but it is connected to ground on the board. My crystal oscillator didn’t generate a clock signal, when pin 1 was connected to GND, although it normally shouldn’t matter.

Still, there was a persistent problem with the external 1MB RAM. It was detected by mtest but depending on the Transputer-type used and some randomness, it never was checked as being ok.
Replacing some capacitors and strengthening some ground traces helped but it’s still not clear what the real reason was.

Here’s the back of the card – looking like a snake-pit now 😉

AVM B1

AVM B1 hacking

February 27, 2008 Axel Leave a comment

Intro

Transputers were created to control everything. They were not just CPUs… they could do the video output, control interfaces or even storage devices. So no wonder there were ISDN and SCSI controllers available using transputers.

One of those transputer-sporting controllers was the AVM B1 active ISDN card. Back in the PC-AT days, handling the ISDN protocol and traffic could easily bring down your super-cool 80386/25 without a problem, especially if this machine should also fulfill server tasks.
So active (vs. passive) ISDN cards were the cure to that issue. They featured a CPU of their own with some RAM to buffer the data coming in at the maximum ultra-fast rate of 128kbps 😉

In case of the the AVM B1 the CPU was a transputer (T400) and that had reign over a whopping 1MB of RAM! When the card was installed and the DOS driver booted, it actually loaded the transputer code onto the card like any normal transputer card would be fed with code – behaving like an Inmos B004 card and even using the same port addresses.
So in fact, the AVM B1 is a transputer card featuring an ISDN-part connected to one of the transputers links.

Using the usual tools for finding and checking a B004 compatible card shows this

> ispy | mtest Using 150 ispy 3.21 | mtest 3.21 # Part rate Link# [ Link0 Link1 Link2 Link3 ] RAM,cycle 0 T400b-20 43k 0 [ HOST ... ... ... ] 2K,1 1022K,6.

Weapon of choice

Ok, cool – so where do I get this card?

Well, AVM is still very alive-and-kicking but they’re not building these cards (using transputers) anymore… even if they wanted to, Inmos/SGS killed the transputer back in 1993. So eBay is your friend.

Anything to watch out for?

Yes! AVM build(s) 4 major versions of the B1: V1 to V4.
V1.x – Available as ISA and MCA version. The perfect choice! Everything important is socketed, no SMD parts.
V2.x – ISA version only. CPU & RAM is SMD. Ready to play with but not much to mod.
V3.x – ISA & PCI version. Updated version, same features like V2.x
V4.x – PCI version only. No transputer anymore. “StrongT” Controller… might hint towards a StrongARM based thingy.

Again: If you want to do all the hacks described here you have to get a Version 1.x card!

Enhance it! This is the easy part…

Ok, so I assume you fought hard to get a V1.x B1… it should look like this:
(If you acquired an V2.0 card which is smaller and has lots of SMD parts on it, check out Jonathan Schillings page (German), who did all the mods described here with a V2.0 card)

If you have your card in front of you, you might spot some differences. These are the first two and most obvious “mods”:

Change the T400 CPU (e.g. to a T425 or even T800)
Add more RAM

The T400 is OK to begin playing with this card, but it only offers 2K internal RAM (vs. 4k in the T425/800) as well as it has only 2 links: One connected to the C012 (and this going to the ISA interface) and one is available. I was under the impression, that AVM might use the other link to interface to the ISDN part, but that seems to be memory-mapped.
Changing to a T425 gives you more internal RAM (=speed) and the possibility to use 3 external links to talk to more connected transputers.
A T800 would be the top-of-the-hill, featuring an FPU which will speed up your Mandelbrot tremendously.

So here’s my T425 which replaced the stock T400. At about 8-10 Euros you should be able to get one at ePay…

Next up, the RAM. Albeit the standard 1MB are plenty enough for nearly all fooling-around you might plan, there’s another Axel-Law to be followed: “If there’s an empty socket, fill it!”.
Also if you’re going serious and think about running the Helios OS on this card, you’ll better have 2MB!
You need to get eight 256Kx4 chips – they’re pretty common. They should be faster than 100ns… you’ll read later why.

The eagle-eyed reader might spot the different makers of the RAM chips. That’s because I’ve salvaged 2 old ISA-VGA cards (each 512k) for the chips. All are spec’ed at 80ns.

Another run of the transputer find/check-tools now shows this

> ispy | mtest

Using 150 ispy 3.21 | mtest 3.21 # Part rate Link# [ Link0 Link1 Link2 Link3 ] RAM,cycle 0 T425b-20 43k 0 [ HOST ... ... ... ] 4K,1 2044K,6.

Not bad, huh? But there’s room for improvement… the RAM is accessed extremely slow, set to 6 clock cycles which is very conservative, even for 100ns RAM parts.

Faster RAM – The not-so-easy part…

Ok, up to here it was a piece of cake, wasn’t it? Now we’re switching to hard-core mode 😉

RAM-Access speed-up

For this you’ll need

Some soldering know-how – and a solder-iron of course
A calm hand
A continuity-tester or multimeter
A thin cutter
the pinout of a transputer (available in the data sheet (PDF))

As said before, the RAM access is very slow. It’s set to 6 clock cycles which is recommended for 150ns parts even at 20MHz. So for a start we should be safe going down to 5 cycles even with the standard 100ns RAM chips…
The RAM is controlled by the transputer itself – something the Intel-World introduced with the AMD Opteron years later!

When booting, the transputer checks how his “MemConfig” pin (position C8) is connected to the MemAD[3-7] pins to determine the RAM speed. The AVM B1 has its “MemConfig” connected to MemAD7 (position K10) which we want to change to MemAD6 (J8) in the first step.
The AVM B1 is a 4-Layer card and unfortunately the wire connecting those two pins is running in the 2nd layer from the back.

To find the trace we have to cut, hold the card in front of you looking at the component-side – like the first picture on this page. Now flip it vertically. You’re looking at the solder-side, the external connectors pointing to the left.
A closer look at the transputer pins shows you where to cut and the wire connecting “MemConfig” with “MemAD6” – Pin A1 is in the upper left corner, counting down[123456789,10], letters right [ABCDEFGHJK]!

The cutting is a delicate thing to do. So be very careful not to cut too deep. I did it by cutting carefully once or twice and then checking with a continuity-tester if MemConfig and MemAD7 are still connected. Repeat until the connection is broken.
If everything went fine solder a wire between the two pins. Don’t make the wire too short, so we can change/move it anytime later. Another test shows this now:

Using 150 ispy 3.23 | mtest 3.22 # Part rate Link# [ Link0 Link1 Link2 Link3 ] RAM,cycle 0 T425b-20 43k 0 [ HOST ... ... ... ] 4K,1 2044K,5.

Yay! RAM’s accessed a bit faster now.

If that works and you’re like me (squeezing out the last drip of everything) you can try connecting to MemAD5 (J9). It worked for me.

Faster Link Speed – Not for the fearsome!

The next thing being rather sub-optimal is the link-speed… 43k/s is dran slow.

Using 150 ispy 3.23 | mtest 3.22 # Part rate Link# [ Link0 Link1 Link2 Link3 ] RAM,cycle 0 T425b-20 43k 0 [ HOST ... ... ... ] 4K,1 2044K,5.

That’s because it’s locked to 10Mbit/s by AVMs design even 20Mbit/s would be possible. Again, the transputer gets its configuration during boot-time via special pins. In this case LinkSpecial(A2), Link0Special(B4) and Link123Special(A4).

Not a big deal, but in case of the AVM B1 it’s not solvable by simply putting those pins high or low. That damn card is -again- a multilayer card and one of those layers is a ground-layer. No way in cutting a trace here.
The only solution is an in-between socket… a calm hand and pincers >:-)

Ok, first you have to get another 84-pin socket. It’s not so easy anymore to find those… luckly, I had one spare collecting dust.

You might find an alternative socket meant for a Motorola 68881/2 FPU – but make sure it also has the inner pin-rows connected. Normally the 68881/2 has 8 pins less!
Another possibillity would be making a socket by glueing 10×1 pin-rows together. Not pretty but should do the job.

For the second step, you’ll need a caliper and (again) the transputer pinout. Orientate the socket so that pin-1 is in the upper left corner (the picture above shows this by the angled-corner in the center of the socket).
Now identify the pins LinkSpecial(A2), Link123Special(A4) and Link0Special(B4) as well as one VCC-Pin of your choice (I went for C2). We need to connect those 4 pins, pulling all Link[n]Specials high… which gives us 20Mbit/s link speed!

Note: If you plan to use the B1’s external links, you might consider not to change the external link-speed – read more about this in the next chapter.
In this case do not change Link123Special(A4).

So carefully cut the thin part of the pins A2, A4 (see note above!) and B4. Use a rasp/file to shorten the pin down to the thicker base (so the remaining part can’t connect to the original socket).
This is how it looks already having A4 & B4 cut off, A2’s still due (all marked red) – Do not cut the VCC-pin (C2, marked blue)! :

When everything’s nicely cut, use a wire to connect them together – it’s a bit tricky to solder between the pins, so use a fine tip.
When you’re done, the socket should look like this:

Now double check the modded pins for shorts to their neighbours!! Not doing so might kill your transputer/card!!

Cool! Were half done. For the third step we need to adjust the other side of the link accordingly. “The other side” is the Inmos C012 link-adaptor sitting in the lower right corner of the card -close to the ISA connector- labeled “IMSC012-P20S”.
Identify pin-15 and use a thin caliper to cut its leg as close to the board as space allows it. Bend the remaining leg up and check that there’s no connection to the card anymore.
Now solder a wire going from pin-15 to some VCC source. I’ve chosen Pin-20 of the 74ALS245 next to the C012. This is how it looks on my card:

[Note: Make your wire long enough so you can reach some GND pin with it. So you can reverse the mod easily.]

We’re nearly there! For the forth and last step, plug your transputer into your in-between socket and the whole thing into the original socket on the card like this:

Done! If everything was done right the usual tools should give you some serious number (well, it’s still far away from the theoretical 1.7Mbit/s, but at least 8.8 times faster than before):

Using 150 ispy 3.23 | mtest 3.22 # Part rate Link# [ Link0 Link1 Link2 Link3 ] RAM,cycle 0 T425b-20 378k 0 [ HOST ... ... ... ] 4K,1 2044K,5.

378k/s is faster than my crappy Gerlach-card (@239k), even the AVM is also just using 8 data-lines of the ISA bus (being a 16-bit card it only uses 4 lines from the AT bus… for IRQs 10-13).

So… what else can be done?

The external Connector

The AVM B1 v1.x cards feature a mysterious (green) connector:

It’s undocumented… up to now 😉 I just started tracing all the connections, but I’m happy to say that even AVM did everything possible to cripple the B1 card, they did not dumb it down completely:

Link[123] & Reset (not inverted!) are brought to the outside!! Error and Analyse are hold to GND, though.

Note: That said, AVM wouldn’t been AVM if they didn’t save a dime… the external links are buffered (at least) by a comparably slow 74BCT541 octal buffer.
This offers a signal propagation delay of ~9ns while INMOS recommended to use “F” type buffers, which offer a speed of about 3-4ns. So 20mbps are too fast for this chip. 10mbps should work though.

Here are my findings so far: [work in progress]

I started counting pins from the transputer, zig-zag, downwards. Interesting things coloured green.

1 2 o o reset o o o o o o o o o o PEB2070o o (to its pin 10) Link3Out o o Link2Out o o Link1Out o o Link3In o o Link2In o o Link1In o o GND o o o o GND o o o o 33 34

GeekDot